This application relates to circuit boards to which integrated circuit (IC) chips may be mounted, and particularly to circuit boards for receiving custom chips, wherein the boards have standardized form factors that allow the chips to be tested in a standard testing apparatus.
IC chips are employed in a wide variety of electronic products including household appliances, vehicles, computers and computer peripheral equipment. As electronic products become smaller, less expensive and more complex, the need for IC chips in such products increases. Customarily, IC chip manufacturers design IC chips to perform specific functions, and market custom versions of those chips to individual original equipment manufacturers (OEM) of the electronic equipment. For example, the manufacturer of an IC chip designed for read/write circuits in a magnetic disk drive might market different versions of the same circuit, and hence of the same chip design, to different disk drive manufacturers. Each disk drive manufacturer receives a version of the chip design that is customized for the needs of that manufacturer. Often, the differences in various chip versions includes differences in pad layout and chip size.
It is important to the manufacturing and marketing processes that all versions of the chip be tested to make certain that the chips perform as required by the OEM customer. Thus, where an OEM customer desires a custom modification of an existing chip, even that custom modification must be tested. However, changing chip layout designs, as is often the case in custom modification of IC chips, results in the proliferation of different versions of the chip size and pad layout (xe2x80x9cfootprintxe2x80x9d), leading to difficulties in the testing of the several chip versions in a standard test device. The present invention is directed to a test board that provides a standard pad and size layout (footprint) to a test machine, yet accommodates IC chips of varying footprints and custom design. As a result, custom chips and chips with altered layout (footprints) can be tested employing the test board according to the present invention.
While the present invention will be described in connection with IC chips having solder bump contacts and conductive pads on the test board arranged in a pattern to receive the bump contacts, it is understood the invention is applicable to other forms of contact connection including area grid arrays, compliant lead contacts on chips receivable on conductive pads as well as insertable contacts such as bayonet and knife contacts receivable in conductive apertures.
A printed wiring board according to the present invention receives a custom integrated circuit chip and provides connection between the chip and a standard footprint layout, such as for a test apparatus. The board includes an insulating substrate that defines a chip receiving region and a separated layout connection region. A plurality of chip connectors, such as bump contact pads, are on one side of the substrate within the chip receiving region. The chip connectors are arranged in a pattern for connection to various custom integrated circuit chips. A plurality of layout connectors are in the layout connection region of the board. At least some of the layout connectors are on the same side of the board as the chip connectors and all of the layout connectors are arranged in a standard footprint layout, such as one accommodating a test apparatus. A plurality of circuit traces on the same side of the substrate as the chip connectors provide electrical connection between individual ones of the chip connectors in the chip receiving region and individual ones of the layout connectors in the layout connection region. A solder stop on the substrate extends over the circuit traces between the chip receiving region and the layout connection region. A plurality of apertures extend through the substrate in the chip receiving region, and a thermally conductive heat sink on the side of the substrate opposite the chip connectors is thermally connected to the plurality of apertures. In use, a chip mounted to the board in the chip receiving region and connected to the chip connectors is mounted by the solder bump contacts which melt and fuse to the chip connectors (contact pads) on the board. The solder stop confines the melted solder to the region of the chip connectors to prevent the bump contacts from deforming and wicking along the traces, thereby preventing collapsing of the bump contacts. A thermally conductive paste extends through the apertures to thermally connect the chip to the heat sink.
In some embodiments, plated holes through the heat sink connect the heat sink to the apertures, and a seal is positioned over the heat sink closing the plated holes. In some embodiments the layout connectors are on both sides of the substrate with plated holes connecting the layout connectors on opposite sides of the substrate.